A high-speed data transmission circuit typically multiplexes several lower-speed signals together to generate output data signals at an output bit rate. An existing data transmission circuit 100 is shown in FIG. 1. A multi-phase clock generator 112 generates clock signals 114. The clock signals 114 have equal phase spacing from one another and each has a frequency that is quarter of the output bit rate. The clock signals 114 are used to drive a multiplexer 116 to couple one of the input data signals 110, having a bit rate that is one quarter of the output bit rate, onto an output 126 and thereby generate output data signals having the output bit rate. Each input data signal 110 is driven onto output 126, in turn, as the clock signals 114 cycle through their respective phases. For example, driver 120a and its associated AND gate 118a drive input data signal d0 110a onto multiplexer output m0 122 when clock signal phi0 114a is a logical true and clock signal phi1 114b is a logical false. Drivers 120b, 120c and 120d perform a similar function for input data signals d1 110b, d2 110c and d3 110d based on the clock signals 114. The multiplexer output m0 122 is amplified by output transmission driver 124 to generate the output data signals on the output 126.
In the data transmission circuit 100, and in high-speed data transmission circuits in general, mismatches in components and wiring may lead to an imbalance between the phases of the clock signals 114. These mismatches include mismatches in the clock generator 112, which result in the clock signals 114 not having equal phase spacing, mismatches in drivers and wiring used for distributing the clock signals 114, and mismatches in the multiplexer 116. The mismatches give rise to timing variations. The timing variations, in turn, may result in an output data signal having one or more bit cells that are too long or too short in duration. Such variations in one or more bits in the output data signals are a source of deterministic jitter and degrade timing margins for a link between the data transmission circuit 100 and a corresponding receiver. There is a need, therefore, for an improved data transmission circuit in order to reduce deterministic jitter in output data signals.
Like reference numerals refer to corresponding parts throughout the drawings.